April 2018 - Anl-intel-lrz-knr - mailman3.cels.anl.gov

Re: [Anl-intel-csa] Number of simulation cycles
by Bertoni, Colleen 30 Apr '18

30 Apr '18

Thanks for all the information about the memory system!   An additional comment about the .stat file and memory performance: I’ve found it useful to check the .stat file and make sure that work is spread over all cache banks (thank you for adding this in the .stat file!). I was looking at a loop that initialized an array (so just stored values), and noticed that if the code was only ever storing to memory addresses that were in two cache banks, adding more than 2 workers didn’t improve the bandwidth. My conclusion was that if we’re not accessing all 16 cache banks, bandwidth is limited by the number of cache banks we’re accessing. Have other people seen this/is this a correct conclusion? Thank you, Colleen Bertoni ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov> on behalf of Jin, Zheming <zjin(a)anl.gov> Sent: Monday, April 30, 2018 6:43 AM To: Tannenbaum, Barry M; Applencourt, Thomas; Finkel, Hal J.; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Number of simulation cycles HI Barry, I remember the .stat file shows the number of unaligned accesses. Users would like to know the locations of unaligned accesses if they may improve the performance of a kernel. I feel it is helpful to report warnings about unaligned cacheline and memory accesses during compile, simulation, and hardware run time. Thank you for describing the general rule. zheming ________________________________ From: Tannenbaum, Barry M <barry.m.tannenbaum(a)intel.com> Sent: Sunday, April 29, 2018 3:04:27 PM To: Jin, Zheming; Applencourt, Thomas; Finkel, Hal J.; anl-intel-csa(a)jlse.anl.gov Subject: RE: [Anl-intel-csa] Number of simulation cycles As a general rule: · For best performance, streaming memory accesses should be cacheline (64-byte) aligned. If a streaming access is not cacheline aligned, the initial request to the memory subsystem will be limited to get to a cacheline boundary. So you’ll end up with extra requests to the memory subsystem. Note that the interface between the simulator and the memory model is changing, but my guess is that it just means that the code for handling cacheline splits moves down from the simulator to the memory model. · Memory accesses should always be naturally aligned I can certainly add warnings about non-cacheline aligned streaming accesses and any memory access that are not naturally aligned if you’d like. From: Jin, Zheming [mailto:[email protected]] Sent: Friday, April 27, 2018 6:23 PM To: Applencourt, Thomas <tapplencourt(a)anl.gov>; Finkel, Hal J. <hfinkel(a)anl.gov>; Tannenbaum, Barry M <barry.m.tannenbaum(a)intel.com>; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Number of simulation cycles In OpenCL SDK for FPGA, when an array allocated for the device is not aligned, users will see warning message when running an application on the FPGA. When a pointer is not restricted in a kernel, users will see another warning message when the kernel is compiled. So they could be helpful message for CSA. ________________________________ From: Applencourt, Thomas Sent: Friday, April 27, 2018 5:01:31 PM To: Finkel, Hal J.; Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles I confirm that from my experiment, this behavior comes from the memory model. But after talking to Eliot, it seems to be a feature, not a bug. If I remember correctly, the main reason is that the memory state of the host change from one simulation to the other. If you align memories and do large memories accesses (to have a consistent behavior of the hash function used by the memory subsystem) you should get relatively similar number of cycles. Thomas, PS: If you read me Elliot, I'm sorry I think butchered the explanations you gave me. Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036 ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov<mailto:[email protected]>> on behalf of Hal Finkel <hfinkel(a)anl.gov<mailto:[email protected]>> Sent: Friday, April 27, 2018 15:31 To: Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles FWIW, not to preclude useful investigation, but the last time that this came up, Kent (I think) said that this can be caused by the memory model because of alignment differences of the allocated memory. If you turn off the memory model, are the cycle times still non-deterministic? -Hal On 04/27/2018 03:28 PM, Tannenbaum, Barry M wrote: Yes, it should give you exactly the same number of cycles everytime. Can you give me a (preferably small) example that shows this? From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 3:35 PM To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] Number of simulation cycles We know that the number of cycles in the CSA simulation report is not always the same for multiple runs of a program. Is it possible to produce the same number for each run of a program in simulation ? Thanks _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Number of simulation cycles
by Jin, Zheming 30 Apr '18

30 Apr '18

HI Barry, I remember the .stat file shows the number of unaligned accesses. Users would like to know the locations of unaligned accesses if they may improve the performance of a kernel. I feel it is helpful to report warnings about unaligned cacheline and memory accesses during compile, simulation, and hardware run time. Thank you for describing the general rule. zheming ________________________________ From: Tannenbaum, Barry M <barry.m.tannenbaum(a)intel.com> Sent: Sunday, April 29, 2018 3:04:27 PM To: Jin, Zheming; Applencourt, Thomas; Finkel, Hal J.; anl-intel-csa(a)jlse.anl.gov Subject: RE: [Anl-intel-csa] Number of simulation cycles As a general rule: · For best performance, streaming memory accesses should be cacheline (64-byte) aligned. If a streaming access is not cacheline aligned, the initial request to the memory subsystem will be limited to get to a cacheline boundary. So you’ll end up with extra requests to the memory subsystem. Note that the interface between the simulator and the memory model is changing, but my guess is that it just means that the code for handling cacheline splits moves down from the simulator to the memory model. · Memory accesses should always be naturally aligned I can certainly add warnings about non-cacheline aligned streaming accesses and any memory access that are not naturally aligned if you’d like. From: Jin, Zheming [mailto:[email protected]] Sent: Friday, April 27, 2018 6:23 PM To: Applencourt, Thomas <tapplencourt(a)anl.gov>; Finkel, Hal J. <hfinkel(a)anl.gov>; Tannenbaum, Barry M <barry.m.tannenbaum(a)intel.com>; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Number of simulation cycles In OpenCL SDK for FPGA, when an array allocated for the device is not aligned, users will see warning message when running an application on the FPGA. When a pointer is not restricted in a kernel, users will see another warning message when the kernel is compiled. So they could be helpful message for CSA. ________________________________ From: Applencourt, Thomas Sent: Friday, April 27, 2018 5:01:31 PM To: Finkel, Hal J.; Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles I confirm that from my experiment, this behavior comes from the memory model. But after talking to Eliot, it seems to be a feature, not a bug. If I remember correctly, the main reason is that the memory state of the host change from one simulation to the other. If you align memories and do large memories accesses (to have a consistent behavior of the hash function used by the memory subsystem) you should get relatively similar number of cycles. Thomas, PS: If you read me Elliot, I'm sorry I think butchered the explanations you gave me. Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036 ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov<mailto:[email protected]>> on behalf of Hal Finkel <hfinkel(a)anl.gov<mailto:[email protected]>> Sent: Friday, April 27, 2018 15:31 To: Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles FWIW, not to preclude useful investigation, but the last time that this came up, Kent (I think) said that this can be caused by the memory model because of alignment differences of the allocated memory. If you turn off the memory model, are the cycle times still non-deterministic? -Hal On 04/27/2018 03:28 PM, Tannenbaum, Barry M wrote: Yes, it should give you exactly the same number of cycles everytime. Can you give me a (preferably small) example that shows this? From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 3:35 PM To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] Number of simulation cycles We know that the number of cycles in the CSA simulation report is not always the same for multiple runs of a program. Is it possible to produce the same number for each run of a program in simulation ? Thanks _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Number of simulation cycles
by Tannenbaum, Barry M 29 Apr '18

29 Apr '18

I believe one additional thing that happens is the CSA simulator by default is it will generate a "loads" file on the first run, and use that for feedback placement of memory references on RAFs for successive runs. I don't believe that the simple memory model uses the .loads file. From: Glossop, Kent Sent: Friday, April 27, 2018 9:06 PM To: Jin, Zheming <zjin(a)anl.gov>; Applencourt, Thomas <tapplencourt(a)anl.gov>; Finkel, Hal J. <hfinkel(a)anl.gov>; Tannenbaum, Barry M <barry.m.tannenbaum(a)intel.com>; anl-intel-csa(a)jlse.anl.gov Subject: RE: [Anl-intel-csa] Number of simulation cycles Alignment in this case means alignment of memory relative to cache line boundaries. On one run, you may have an input array at one address, and on a different run, at a different address. Even old linux systems will often see address changes based on things like environment variable state that changes between successive runs. More modern ones are apparently increasingly trying to give different addresses on different runs for security reasons. Different addresses will interact differently in the cache system, depending on hashing functions, and depending on relative alignment to the start of a cache line. If you have graphs that do not use the memory model, that give different cycle counts, it should be investigated. If you have programs where the addresses of everything the CSA touches are identical, but gives different answers run to run, that should also be investigated. I believe one additional thing that happens is the CSA simulator by default is it will generate a "loads" file on the first run, and use that for feedback placement of memory references on RAFs for successive runs. If this is what is going on, you should see stable runs from the second, onward. (As with assuming minimum latency for LICs and larger default buffering than HW, this is a stand-in for an as-yet-to-exist arrangement, which is considerably better static placement of memory ops onto RAFs.) As with the other two approximations, this is expected to be removed once the appropriate transforms are in place. Kent From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 5:23 PM To: Applencourt, Thomas <tapplencourt(a)anl.gov<mailto:[email protected]>>; Finkel, Hal J. <hfinkel(a)anl.gov<mailto:[email protected]>>; Tannenbaum, Barry M <barry.m.tannenbaum(a)intel.com<mailto:[email protected]>>; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles In OpenCL SDK for FPGA, when an array allocated for the device is not aligned, users will see warning message when running an application on the FPGA. When a pointer is not restricted in a kernel, users will see another warning message when the kernel is compiled. So they could be helpful message for CSA. ________________________________ From: Applencourt, Thomas Sent: Friday, April 27, 2018 5:01:31 PM To: Finkel, Hal J.; Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles I confirm that from my experiment, this behavior comes from the memory model. But after talking to Eliot, it seems to be a feature, not a bug. If I remember correctly, the main reason is that the memory state of the host change from one simulation to the other. If you align memories and do large memories accesses (to have a consistent behavior of the hash function used by the memory subsystem) you should get relatively similar number of cycles. Thomas, PS: If you read me Elliot, I'm sorry I think butchered the explanations you gave me. Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036 ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov<mailto:[email protected]>> on behalf of Hal Finkel <hfinkel(a)anl.gov<mailto:[email protected]>> Sent: Friday, April 27, 2018 15:31 To: Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles FWIW, not to preclude useful investigation, but the last time that this came up, Kent (I think) said that this can be caused by the memory model because of alignment differences of the allocated memory. If you turn off the memory model, are the cycle times still non-deterministic? -Hal On 04/27/2018 03:28 PM, Tannenbaum, Barry M wrote: Yes, it should give you exactly the same number of cycles everytime. Can you give me a (preferably small) example that shows this? From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 3:35 PM To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] Number of simulation cycles We know that the number of cycles in the CSA simulation report is not always the same for multiple runs of a program. Is it possible to produce the same number for each run of a program in simulation ? Thanks _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Number of simulation cycles
by Tannenbaum, Barry M 29 Apr '18

29 Apr '18

As a general rule: * For best performance, streaming memory accesses should be cacheline (64-byte) aligned. If a streaming access is not cacheline aligned, the initial request to the memory subsystem will be limited to get to a cacheline boundary. So you'll end up with extra requests to the memory subsystem. Note that the interface between the simulator and the memory model is changing, but my guess is that it just means that the code for handling cacheline splits moves down from the simulator to the memory model. * Memory accesses should always be naturally aligned I can certainly add warnings about non-cacheline aligned streaming accesses and any memory access that are not naturally aligned if you'd like. From: Jin, Zheming [mailto:[email protected]] Sent: Friday, April 27, 2018 6:23 PM To: Applencourt, Thomas <tapplencourt(a)anl.gov>; Finkel, Hal J. <hfinkel(a)anl.gov>; Tannenbaum, Barry M <barry.m.tannenbaum(a)intel.com>; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Number of simulation cycles In OpenCL SDK for FPGA, when an array allocated for the device is not aligned, users will see warning message when running an application on the FPGA. When a pointer is not restricted in a kernel, users will see another warning message when the kernel is compiled. So they could be helpful message for CSA. ________________________________ From: Applencourt, Thomas Sent: Friday, April 27, 2018 5:01:31 PM To: Finkel, Hal J.; Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles I confirm that from my experiment, this behavior comes from the memory model. But after talking to Eliot, it seems to be a feature, not a bug. If I remember correctly, the main reason is that the memory state of the host change from one simulation to the other. If you align memories and do large memories accesses (to have a consistent behavior of the hash function used by the memory subsystem) you should get relatively similar number of cycles. Thomas, PS: If you read me Elliot, I'm sorry I think butchered the explanations you gave me. Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036 ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov<mailto:[email protected]>> on behalf of Hal Finkel <hfinkel(a)anl.gov<mailto:[email protected]>> Sent: Friday, April 27, 2018 15:31 To: Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles FWIW, not to preclude useful investigation, but the last time that this came up, Kent (I think) said that this can be caused by the memory model because of alignment differences of the allocated memory. If you turn off the memory model, are the cycle times still non-deterministic? -Hal On 04/27/2018 03:28 PM, Tannenbaum, Barry M wrote: Yes, it should give you exactly the same number of cycles everytime. Can you give me a (preferably small) example that shows this? From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 3:35 PM To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] Number of simulation cycles We know that the number of cycles in the CSA simulation report is not always the same for multiple runs of a program. Is it possible to produce the same number for each run of a program in simulation ? Thanks _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Number of simulation cycles
by Glossop, Kent 27 Apr '18

27 Apr '18

Alignment in this case means alignment of memory relative to cache line boundaries. On one run, you may have an input array at one address, and on a different run, at a different address. Even old linux systems will often see address changes based on things like environment variable state that changes between successive runs. More modern ones are apparently increasingly trying to give different addresses on different runs for security reasons. Different addresses will interact differently in the cache system, depending on hashing functions, and depending on relative alignment to the start of a cache line. If you have graphs that do not use the memory model, that give different cycle counts, it should be investigated. If you have programs where the addresses of everything the CSA touches are identical, but gives different answers run to run, that should also be investigated. I believe one additional thing that happens is the CSA simulator by default is it will generate a "loads" file on the first run, and use that for feedback placement of memory references on RAFs for successive runs. If this is what is going on, you should see stable runs from the second, onward. (As with assuming minimum latency for LICs and larger default buffering than HW, this is a stand-in for an as-yet-to-exist arrangement, which is considerably better static placement of memory ops onto RAFs.) As with the other two approximations, this is expected to be removed once the appropriate transforms are in place. Kent From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 5:23 PM To: Applencourt, Thomas <tapplencourt(a)anl.gov>; Finkel, Hal J. <hfinkel(a)anl.gov>; Tannenbaum, Barry M <barry.m.tannenbaum(a)intel.com>; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Number of simulation cycles In OpenCL SDK for FPGA, when an array allocated for the device is not aligned, users will see warning message when running an application on the FPGA. When a pointer is not restricted in a kernel, users will see another warning message when the kernel is compiled. So they could be helpful message for CSA. ________________________________ From: Applencourt, Thomas Sent: Friday, April 27, 2018 5:01:31 PM To: Finkel, Hal J.; Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles I confirm that from my experiment, this behavior comes from the memory model. But after talking to Eliot, it seems to be a feature, not a bug. If I remember correctly, the main reason is that the memory state of the host change from one simulation to the other. If you align memories and do large memories accesses (to have a consistent behavior of the hash function used by the memory subsystem) you should get relatively similar number of cycles. Thomas, PS: If you read me Elliot, I'm sorry I think butchered the explanations you gave me. Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036 ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov<mailto:[email protected]>> on behalf of Hal Finkel <hfinkel(a)anl.gov<mailto:[email protected]>> Sent: Friday, April 27, 2018 15:31 To: Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Number of simulation cycles FWIW, not to preclude useful investigation, but the last time that this came up, Kent (I think) said that this can be caused by the memory model because of alignment differences of the allocated memory. If you turn off the memory model, are the cycle times still non-deterministic? -Hal On 04/27/2018 03:28 PM, Tannenbaum, Barry M wrote: Yes, it should give you exactly the same number of cycles everytime. Can you give me a (preferably small) example that shows this? From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 3:35 PM To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] Number of simulation cycles We know that the number of cycles in the CSA simulation report is not always the same for multiple runs of a program. Is it possible to produce the same number for each run of a program in simulation ? Thanks _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Number of simulation cycles
by Jin, Zheming 27 Apr '18

27 Apr '18

In OpenCL SDK for FPGA, when an array allocated for the device is not aligned, users will see warning message when running an application on the FPGA. When a pointer is not restricted in a kernel, users will see another warning message when the kernel is compiled. So they could be helpful message for CSA. ________________________________ From: Applencourt, Thomas Sent: Friday, April 27, 2018 5:01:31 PM To: Finkel, Hal J.; Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Number of simulation cycles I confirm that from my experiment, this behavior comes from the memory model. But after talking to Eliot, it seems to be a feature, not a bug. If I remember correctly, the main reason is that the memory state of the host change from one simulation to the other. If you align memories and do large memories accesses (to have a consistent behavior of the hash function used by the memory subsystem) you should get relatively similar number of cycles. Thomas, PS: If you read me Elliot, I'm sorry I think butchered the explanations you gave me. Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036 ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov> on behalf of Hal Finkel <hfinkel(a)anl.gov> Sent: Friday, April 27, 2018 15:31 To: Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Number of simulation cycles FWIW, not to preclude useful investigation, but the last time that this came up, Kent (I think) said that this can be caused by the memory model because of alignment differences of the allocated memory. If you turn off the memory model, are the cycle times still non-deterministic? -Hal On 04/27/2018 03:28 PM, Tannenbaum, Barry M wrote: Yes, it should give you exactly the same number of cycles everytime. Can you give me a (preferably small) example that shows this? From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 3:35 PM To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] Number of simulation cycles We know that the number of cycles in the CSA simulation report is not always the same for multiple runs of a program. Is it possible to produce the same number for each run of a program in simulation ? Thanks _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Number of simulation cycles
by Applencourt, Thomas 27 Apr '18

27 Apr '18

I confirm that from my experiment, this behavior comes from the memory model. But after talking to Eliot, it seems to be a feature, not a bug. If I remember correctly, the main reason is that the memory state of the host change from one simulation to the other. If you align memories and do large memories accesses (to have a consistent behavior of the hash function used by the memory subsystem) you should get relatively similar number of cycles. Thomas, PS: If you read me Elliot, I'm sorry I think butchered the explanations you gave me. Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036 ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov> on behalf of Hal Finkel <hfinkel(a)anl.gov> Sent: Friday, April 27, 2018 15:31 To: Tannenbaum, Barry M; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Number of simulation cycles FWIW, not to preclude useful investigation, but the last time that this came up, Kent (I think) said that this can be caused by the memory model because of alignment differences of the allocated memory. If you turn off the memory model, are the cycle times still non-deterministic? -Hal On 04/27/2018 03:28 PM, Tannenbaum, Barry M wrote: Yes, it should give you exactly the same number of cycles everytime. Can you give me a (preferably small) example that shows this? From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 3:35 PM To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] Number of simulation cycles We know that the number of cycles in the CSA simulation report is not always the same for multiple runs of a program. Is it possible to produce the same number for each run of a program in simulation ? Thanks _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Number of simulation cycles
by Hal Finkel 27 Apr '18

27 Apr '18

FWIW, not to preclude useful investigation, but the last time that this came up, Kent (I think) said that this can be caused by the memory model because of alignment differences of the allocated memory. If you turn off the memory model, are the cycle times still non-deterministic? ï¿½-Hal On 04/27/2018 03:28 PM, Tannenbaum, Barry M wrote: > > Yes, it should give you exactly the same number of cycles everytime. > Can you give me a (preferably small) example that shows this? > > ï¿½ > > *From:*anl-intel-csa [mailto:[email protected]] > *On Behalf Of *Jin, Zheming > *Sent:* Friday, April 27, 2018 3:35 PM > *To:* anl-intel-csa(a)jlse.anl.gov > *Subject:* [Anl-intel-csa] Number of simulation cycles > > ï¿½ > > We know that the number of cycles in the CSAï¿½simulation reportï¿½is not > always the sameï¿½for multiple runs of a program. > > Is it possible to produceï¿½the same number for each run of a program in > /simulation /?ï¿½ï¿½ > > ï¿½ > > Thanks > > ï¿½ > > > > _______________________________________________ > anl-intel-csa mailing list > anl-intel-csa(a)lists.jlse.anl.gov > https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Number of simulation cycles
by Tannenbaum, Barry M 27 Apr '18

27 Apr '18

Yes, it should give you exactly the same number of cycles everytime. Can you give me a (preferably small) example that shows this? From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Friday, April 27, 2018 3:35 PM To: anl-intel-csa(a)jlse.anl.gov Subject: [Anl-intel-csa] Number of simulation cycles We know that the number of cycles in the CSA simulation report is not always the same for multiple runs of a program. Is it possible to produce the same number for each run of a program in simulation ? Thanks

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Re: [Anl-intel-csa] Do we need to create latest-id for each release ?
by Kumaran, Kalyan 27 Apr '18

27 Apr '18

Ben is restoring it. Maybe we revisit who has access through the intel-csa-owner Unix group. -Kumar On Apr 27, 2018, at 2:48 PM, Applencourt, Thomas <tapplencourt(a)anl.gov<mailto:[email protected]>> wrote: Everything in `comp` has been deleted. Something happened. Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036 ________________________________ From: anl-intel-csa <anl-intel-csa-bounces(a)lists.jlse.anl.gov<mailto:[email protected]>> on behalf of Jin, Zheming <zjin(a)anl.gov<mailto:[email protected]>> Sent: Friday, April 27, 2018 14:12 To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] Do we need to create latest-id for each release ? This kit is a Software Development Kit for exploration of the CSA, covered under an Intel Restricted Secret Non-Disclosure Agreement (RSNDA). See /soft/restricted/intel_csa/license.pdf for more information. Traceback (most recent call last): File "/soft/restricted/intel_csa/csaenv_backend.py", line 338, in <module> currentCSAenv.setCommand() File "/soft/restricted/intel_csa/csaenv_backend.py", line 231, in setCommand with open(jp(os.environ.get("CSA_ROOT"), "comp", "csa", "latest-id")) as latestIDfile: IOError: [Errno 2] No such file or directory: '/soft/restricted/intel_csa/comp/csa/latest-id' _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa

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