January 2018 - Anl-intel-lrz-knr - mailman3.cels.anl.gov

Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark
by Jin, Zheming 30 Jan '18

30 Jan '18

Hi Arvind, Following your spmd optimization. I added the impact of block size on performance/resource for the example4c. Thank you for your comments. [cid:00793b0c-ad26-40b4-9fec-f58f5a9a2d8e] [cid:ab94daf6-0bf9-4d28-aa4a-57134e154b74] ________________________________ From: Sudarsanam, Arvind <arvind.sudarsanam(a)intel.com> Sent: Thursday, January 25, 2018 11:38:28 AM To: Finkel, Hal J.; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov Subject: RE: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark Hi, I looked at the very first example (example4c) and was able to reproduce the numbers presented here. I went ahead and annotated the loop inside example4c with the spmdization intrinsic and I was able to bring the intel compiler cycles to 504. Annotation: __builtin_csa_spmdization(8,”cyclic”); I can try other test cases as well. Thanks Arvind From: anl-intel-csa [mailto:[email protected]] On Behalf Of Hal Finkel Sent: Wednesday, January 24, 2018 11:15 PM To: Jin, Zheming <zjin(a)anl.gov>; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark Zheming, thanks! It might be easier to look at it this way (negative means our prototype is better, positive means Intel's is better): cycles (intel) cycles (anl) intel speedup example4c 27089 440 -98.38% example4b 8600 418 -95.14% example1 6910 360 -94.79% example7 6025 349 -94.21% example10b 919 350 -61.92% example25 932 378 -59.44% example10a 933 390 -58.20% example21 6776 7567 11.67% example13 1223 1414 15.62% example11 7808 10343 32.47% example9 7422 10210 37.56% example2b 6928 9881 42.62% example24 797 1441 80.80% example14 907 1919 111.58% example2a 785 2053 161.53% example5a 40 214 435.00% example23 920 6456 601.74% example3 938 7164 663.75% example4a 939 7285 675.83% example8 123 2518 1947.15% On 01/24/2018 09:48 PM, Jin, Zheming wrote: The Microsoft Excel spread sheet lists the performance of the prototype compiler (anl) and the Intel CSA compiler (intel) using the OpenMP mode and gcc-loops benchmark. The performance metrics are cycles, static operation count and static lic count. The test files are located at /soft/restricted/intel_csa/apps/gcc-loops. [cid:[email protected]] [cid:[email protected]] [cid:[email protected]] _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark
by Jin, Zheming 30 Jan '18

30 Jan '18

Hi Arvind, I thought that those built-in instrinsics are not supported in the OpenMP offload mode. They are supported actually. They can significantly reduce the cycles from 27089 to 441 for example4c. The resource usage increases from 38 static ops, 53 lic counts to 277 and 446, respectively. For the prototype, the cycle, static ops, and lic counts are 440, 207, and 372, respectively. Thanks, zheming ________________________________ From: Sudarsanam, Arvind <arvind.sudarsanam(a)intel.com> Sent: Thursday, January 25, 2018 11:38:28 AM To: Finkel, Hal J.; Jin, Zheming; anl-intel-csa(a)jlse.anl.gov Subject: RE: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark Hi, I looked at the very first example (example4c) and was able to reproduce the numbers presented here. I went ahead and annotated the loop inside example4c with the spmdization intrinsic and I was able to bring the intel compiler cycles to 504. Annotation: __builtin_csa_spmdization(8,”cyclic”); I can try other test cases as well. Thanks Arvind From: anl-intel-csa [mailto:[email protected]] On Behalf Of Hal Finkel Sent: Wednesday, January 24, 2018 11:15 PM To: Jin, Zheming <zjin(a)anl.gov>; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark Zheming, thanks! It might be easier to look at it this way (negative means our prototype is better, positive means Intel's is better): cycles (intel) cycles (anl) intel speedup example4c 27089 440 -98.38% example4b 8600 418 -95.14% example1 6910 360 -94.79% example7 6025 349 -94.21% example10b 919 350 -61.92% example25 932 378 -59.44% example10a 933 390 -58.20% example21 6776 7567 11.67% example13 1223 1414 15.62% example11 7808 10343 32.47% example9 7422 10210 37.56% example2b 6928 9881 42.62% example24 797 1441 80.80% example14 907 1919 111.58% example2a 785 2053 161.53% example5a 40 214 435.00% example23 920 6456 601.74% example3 938 7164 663.75% example4a 939 7285 675.83% example8 123 2518 1947.15% On 01/24/2018 09:48 PM, Jin, Zheming wrote: The Microsoft Excel spread sheet lists the performance of the prototype compiler (anl) and the Intel CSA compiler (intel) using the OpenMP mode and gcc-loops benchmark. The performance metrics are cycles, static operation count and static lic count. The test files are located at /soft/restricted/intel_csa/apps/gcc-loops. [cid:[email protected]] [cid:[email protected]] [cid:[email protected]] _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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[Anl-intel-csa] `Internal error in fusion code - probably a bug!
by Applencourt, Thomas 29 Jan '18

29 Jan '18

Hi, Using the last release (2018-01-22) the following asm: .text .globl fus .entry fus, hybriddataflow .result .lic .nil out_ctl .param .lic .nil in_ctl .param .lic .i32 n_gathed .lic .i32 n pick32 n, in_ctl, n_gathed, %ign .lic .i32 n01 copy32 %ign, %ign, %ign, n01, n .lic .i32 n11 .lic .i32 n12 copy32 n11, n12, %ign, %ign, n01 .lic .i32 n2 add32 n2, n11, n12 all0 out_ctl, n2 Produce the following error message: allocating csa... Using simulator from /soft/restricted/intel_csa/comp/fsim/2018-01-22-release/libcsasim.so assembling... Internal error in fusion code - probably a bug! SAVE: input, output, log file, command line, console output <type 'exceptions.AttributeError'> 'NoneType' object has no attribute 'statements' csasim warning: Fusion tool failed The attached zip file contains the asm file and the main.cpp needed to reproduce the probable bug. I joined the logfile too. Thank you, Regards, Thomas Applencourt Leadership Computing Facility Argonne National Laboratory Building 240 Office - 1.D.18 9700 S Cass Av., Argonne Il, 60439 (630) 252-0036

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Re: [Anl-intel-csa] function call in OMP target region using Intel CSA compiler
by Tannenbaum, Barry M 29 Jan '18

29 Jan '18

Thanks, Ravi. The only way I know of to work around this with the version of OpenMP/llvm/clang we're currently using is to extract s152s into its own module, compile it to LLVM IR library, and then link against it. Look at the examples in $CSA_TOP/samples/omp-offload/complex or $CSA_TOP/samples/omp-offload/libtest for examples of how to do this. - Barry From: anl-intel-csa [mailto:[email protected]] On Behalf Of Narayanaswamy, Ravi Sent: Monday, January 29, 2018 5:50 PM To: Jin, Zheming <zjin(a)anl.gov>; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] function call in OMP target region using Intel CSA compiler Currently we don't support it but the plan is to support it. IBM has implemented the support for omp declare target in clang but have not promoted it to llorg. We are waiting for them to push their changes to the open source. From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Monday, January 29, 2018 2:44 PM To: anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: [Anl-intel-csa] function call in OMP target region using Intel CSA compiler Does Intel CSA compiler support function call in the OMP target region as shown below ? I got the compile error about the undefined function s152s. Thanks #pragma omp declare target int s152s(float a[LEN], float b[LEN], float c[LEN], int i) { a[i] += b[i] * c[i]; return 0; } #pragma omp end declare target int s152() { for (int nl = 0; nl < ntimes; nl++) { #pragma omp target map(tofrom: a) map(to: b,c,d,e) { for (int i = 0; i < LEN; i++) { b[i] = d[i] * e[i]; s152s(a, b, c, i); } } } return 0; }

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Re: [Anl-intel-csa] function call in OMP target region using Intel CSA compiler
by Narayanaswamy, Ravi 29 Jan '18

29 Jan '18

Currently we don't support it but the plan is to support it. IBM has implemented the support for omp declare target in clang but have not promoted it to llorg. We are waiting for them to push their changes to the open source. From: anl-intel-csa [mailto:[email protected]] On Behalf Of Jin, Zheming Sent: Monday, January 29, 2018 2:44 PM To: anl-intel-csa(a)jlse.anl.gov Subject: [Anl-intel-csa] function call in OMP target region using Intel CSA compiler Does Intel CSA compiler support function call in the OMP target region as shown below ? I got the compile error about the undefined function s152s. Thanks #pragma omp declare target int s152s(float a[LEN], float b[LEN], float c[LEN], int i) { a[i] += b[i] * c[i]; return 0; } #pragma omp end declare target int s152() { for (int nl = 0; nl < ntimes; nl++) { #pragma omp target map(tofrom: a) map(to: b,c,d,e) { for (int i = 0; i < LEN; i++) { b[i] = d[i] * e[i]; s152s(a, b, c, i); } } } return 0; }

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[Anl-intel-csa] function call in OMP target region using Intel CSA compiler
by Jin, Zheming 29 Jan '18

29 Jan '18

Does Intel CSA compiler support function call in the OMP target region as shown below ? I got the compile error about the undefined function s152s. Thanks #pragma omp declare target int s152s(float a[LEN], float b[LEN], float c[LEN], int i) { a[i] += b[i] * c[i]; return 0; } #pragma omp end declare target int s152() { for (int nl = 0; nl < ntimes; nl++) { #pragma omp target map(tofrom: a) map(to: b,c,d,e) { for (int i = 0; i < LEN; i++) { b[i] = d[i] * e[i]; s152s(a, b, c, i); } } } return 0; }

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Re: [Anl-intel-csa] ANL Prototype Compiler
by Hal Finkel 25 Jan '18

25 Jan '18

FYI: This information has been posted to a page on our confluence (we'll update it there): https://wiki.jlse.anl.gov/display/intelcsa/ALCF+Prototype+Compiler -Hal On 01/24/2018 05:47 PM, Hal Finkel wrote: > > Hi, everyone, > > To follow-up on our call last week, I've attached the slides. I've > installed a version of the compiler in > /soft/restricted/intel_csa/apps/anl-llvm > > > How To Use > > Source /soft/restricted/intel_csa/apps/anl-llvm/setup.bash (you should > source /soft/restricted/intel_csa/csasetup.bash first, but if you > forget, it will source it for you). > > > Direct Compilation > > There's a csa-clang wrapper script. You can use it to compile from > source code to CSA assembly: > > $ csa-clang -O3 -S -o Step10_orig.s Step10_orig.c > > You need to optimize (the compiler does not yet support local stack > accesses) and remember to use -ffast-math if you'd like non-IEEE > floating-point optimizations or -ffp-contract=fast to just enable > aggressive FMA formation. > > To get optimization remarks, you need to know that the relevant > transformation name is "csa-pipeline-loops", and so you can run with: > > $ csa-clang -O3 -S -o Step10_orig.s Step10_orig.c -Rpass=csa-pipeline-loops -Rpass-missed=csa-pipeline-loops -Rpass-analysis=csa-pipeline-loops > *Step10_orig.c:32:2: **remark: **estimated per-worker loop metrics: ops: 42, sp-fma ops: 38, dp-fma > ops: 0, memory ops: 4, bytes in: 16, bytes out: 0 > [-Rpass-analysis=csa-pipeline-loops]* > for ( j = 0; j < count1; j++ ) { > *^* > *Step10_orig.c:47:12: **remark: **the legality of pipelining is predicated on a lack of control > divergence [-Rpass-analysis=csa-pipeline-loops]* > zi = zi + f * dzc; > *^* > *Step10_orig.c:46:12: **remark: **the legality of pipelining is predicated on a lack of control > divergence [-Rpass-analysis=csa-pipeline-loops]* > yi = yi + f * dyc; > *^* > *Step10_orig.c:45:12: **remark: **the legality of pipelining is predicated on a lack of control > divergence [-Rpass-analysis=csa-pipeline-loops]* > xi = xi + f * dxc; > *^* > *Step10_orig.c:33:18: **remark: **memory access can be streamed [-Rpass-analysis=csa-pipeline-loops]* > dxc = pos1[j].x - xxi; > *^* > *Step10_orig.c:34:18: **remark: **memory access can be streamed [-Rpass-analysis=csa-pipeline-loops]* > dyc = pos1[j].y - yyi; > *^* > *Step10_orig.c:35:18: **remark: **memory access can be streamed [-Rpass-analysis=csa-pipeline-loops]* > dzc = pos1[j].z - zzi; > *^* > *Step10_orig.c:39:16: **remark: **memory access can be streamed [-Rpass-analysis=csa-pipeline-loops]* > m = pos1[j].w; > *^* > *Step10_orig.c:32:2: **remark: **loop pipelined [-Rpass=csa-pipeline-loops]* > for ( j = 0; j < count1; j++ ) { > *^* > > In this case, a non-associative reduction is preventing the generation > of multiple workers. Using -ffast-math will change this: > > $ csa-clang -O3 -S -o Step10_orig.s Step10_orig.c -ffast-math -Rpass=csa-pipeline-loops -Rpass-missed=csa-pipeline-loops -Rpass-analysis=csa-pipeline-loops > *Step10_orig.c:32:2: **remark: **estimated per-worker loop metrics: ops: 31, sp-fma ops: 27, dp-fma > ops: 0, memory ops: 4, bytes in: 16, bytes out: 0 > [-Rpass-analysis=csa-pipeline-loops]* > for ( j = 0; j < count1; j++ ) { > *^* > *Step10_orig.c:33:18: **remark: **memory access can be streamed [-Rpass-analysis=csa-pipeline-loops]* > dxc = pos1[j].x - xxi; > *^* > *Step10_orig.c:34:18: **remark: **memory access can be streamed [-Rpass-analysis=csa-pipeline-loops]* > dyc = pos1[j].y - yyi; > *^* > *Step10_orig.c:35:18: **remark: **memory access can be streamed [-Rpass-analysis=csa-pipeline-loops]* > dzc = pos1[j].z - zzi; > *^* > *Step10_orig.c:39:16: **remark: **memory access can be streamed [-Rpass-analysis=csa-pipeline-loops]* > m = pos1[j].w; > *^* > *Step10_orig.c:32:2: **remark: **pipelining can generate at most 8 workers > [-Rpass-analysis=csa-pipeline-loops]* > for ( j = 0; j < count1; j++ ) { > *^* > *Step10_orig.c:32:2: **remark: **loop pipelined [-Rpass=csa-pipeline-loops]* > *Step10_orig.c:32:2: **remark: **loop pipelining will use 8 workers [-Rpass=csa-pipeline-loops]* > > Also, you can use "#pragma omp simd" to mark loops as data-parallel > loops (so long as you don't use the safelen pragma). > > > OpenMP Target Offloading > > You can use OpenMP target offloading to compile and run the associated > code using the CSA simulator. The OpenMP runtime library will find the > CSA simulator using the CSASIM_TOP environmental variable (which > csasetup.bash will set for you). When you compile using OpenMP > offloading, you need to enable OpenMP, and additionally, list CSA as > the OpenMP target. Like this: > > $ clang -O3 -fopenmp -fopenmp-targets=csa -o example7 example7.c -Rpass=csa-pipeline-loops -Rpass-missed=csa-pipeline-loops -Rpass-analysis=csa-pipeline-loops > *example7.c:19:4: **remark: **estimated per-worker loop metrics: ops: 5, sp-fma ops: 0, dp-fma ops: > 0, memory ops: 2, bytes in: 4, bytes out: 4 > [-Rpass-analysis=csa-pipeline-loops]* > for (i=0; i<N; i++){ > *^* > *example7.c:20:14: **remark: **memory access can be streamed with unit stride > [-Rpass-analysis=csa-pipeline-loops]* > a[i] = b[i+x]; > *^* > *example7.c:20:12: **remark: **memory access can be streamed with unit stride > [-Rpass-analysis=csa-pipeline-loops]* > a[i] = b[i+x]; > *^* > *example7.c:19:4: **remark: **pipelining can generate at most 16 workers > [-Rpass-analysis=csa-pipeline-loops]* > for (i=0; i<N; i++){ > *^* > *example7.c:19:4: **remark: **loop pipelined [-Rpass=csa-pipeline-loops]* > *example7.c:19:4: **remark: **loop pipelining will use 16 workers [-Rpass=csa-pipeline-loops]* > > Note that both -fopenmp -fopenmp-targets=csa are used. You can then > run the program: > > $ ./example7 > Using simulator from /soft/restricted/intel_csa/comp/fsim/2018-01-22-release/libcsasim.so > Using simple memory model > example7.c success > > And if you want to dump stats and/or see verbose messages, you can use > the CSA_VERBOSE=1 and/or CSA_DUMP_STATS=1 environmental variables: > > $ CSA_VERBOSE=1 CSA_DUMP_STATS=1 ./example7 > Using simulator from /soft/restricted/intel_csa/comp/fsim/2018-01-22-release/libcsasim.so > Executing OpenMP target region on simulated CSA device 0 > Using simple memory model > Executed OpenMP target region on simulated CSA device 0 in 349 cycles. > example7.c success > $ ls example7-openmp-0-csa0.stat > example7-openmp-0-csa0.stat > > > Misc. Notes > > * To limit the number of workers being generated, you can use: > -mllvm -csa-max-workers=<n> (where setting n = 1 will disable > worker creation). > * To disable loop pipelining, use: -mllvm -disable-csa-pipeline-loops > * The preprocessor will define both __CSA__ and __CSA_ANL__, so you > can use the latter to differentiate this prototype from Intel's > compiler. You can, thus, use #ifndef __CSA_ANL__ in order to guard > use of Intel-specific builtins. > * There is one CSA-specific builtin supported: > __builtin_csa_debugprint(value) (which generated a debugprint > instruction that causes the simulator to print the associated value). > > If you have any questions, please feel free to ask. I'm sure there are > bugs, etc. please feel free to report them. > > -Hal > > P.S. The current build has a bug whereby, when multiple workers are > generated, if there isn't enough work to give each worker at least one > loop iteration, the graph will stall. I'll fix that soon. > > Also, the build I've installed is a debug build, so it'll be a bit > slow to compile things. I'll generate a faster build soon too. > > -- > Hal Finkel > Lead, Compiler Technology and Programming Languages > Leadership Computing Facility > Argonne National Laboratory > > > _______________________________________________ > anl-intel-csa mailing list > anl-intel-csa(a)lists.jlse.anl.gov > https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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[Anl-intel-csa] Please Read - Friday con calls
by Kumaran, Kalyan 25 Jan '18

25 Jan '18

The Friday con calls are open only to Intel and Argonne employees covered by the A21 CITR. They are not open to folks on the PathForward CITR or non Argonne employees on A21 CITR (a few of the E6 lab folks have been added to provide access to the simulator). Please do not discuss A21 information with folks covered by the PathForward CITR. If you would like to know if someone is covered by the A21 CITR please shoot me an email. Also when you join the Skype session please list your name. Last week someone joined as “ANL Guest”. This is not acceptable and we might be forced to stop the call. Sorry. Thanks, Kumar

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Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark
by Hal Finkel 25 Jan '18

25 Jan '18

Thanks! ï¿½-Hal On 01/25/2018 12:27 PM, Sudarsanam, Arvind wrote: > > Hi Hal, > > ï¿½ > > I tried blocked-distribution spmdization and the number of cycles is > 512. No, the performance is not different from using cyclic-distribution. > > ï¿½ > > Thanks > > Arvind > > ï¿½ > > *From:*Hal Finkel [mailto:[email protected]] > *Sent:* Thursday, January 25, 2018 12:46 PM > *To:* Sudarsanam, Arvind <arvind.sudarsanam(a)intel.com>; Jin, Zheming > <zjin(a)anl.gov>; anl-intel-csa(a)jlse.anl.gov > *Subject:* Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler > using gcc-loops benchmark > > ï¿½ > > ï¿½ > > ï¿½ > > On 01/25/2018 11:38 AM, Sudarsanam, Arvind wrote: > > Hi, > > ï¿½ > > I looked at the very first example (example4c) and was able to > reproduce the numbers presented here. > > I went ahead and annotated the loop inside example4c with the > spmdization intrinsic and I was able to bring the intel compiler > cycles to 504. > > ï¿½ > > Annotation: __builtin_csa_spmdization(8,ï¿½cyclicï¿½); > > ï¿½ > > I can try other test cases as well. > > > Thanks! Out of curiosity, because our prototype always uses block > distribution (we haven't implemented cyclic yet), is the performance > different with the Intel compiler with block-distribution spmdization? > > ï¿½-Hal > > > ï¿½ > > Thanks > > Arvind > > ï¿½ > > ï¿½ > > ï¿½ > > ï¿½ > > ï¿½ > > *From:*anl-intel-csa > [mailto:[email protected]] *On Behalf Of > *Hal Finkel > *Sent:* Wednesday, January 24, 2018 11:15 PM > *To:* Jin, Zheming <zjin(a)anl.gov> <mailto:[email protected]>; > anl-intel-csa(a)jlse.anl.gov <mailto:[email protected]> > *Subject:* Re: [Anl-intel-csa] Evaluation of ANL Prototype > Compiler using gcc-loops benchmark > > ï¿½ > > Zheming, thanks! > > ï¿½ > > It might be easier to look at it this way (negative means our > prototype is better, positive means Intel's is better): > > ï¿½ > > > > > cycles (intel) > > > > cycles (anl) > > > > intel speedup > > example4c > > > > 27089 > > > > 440 > > > > -98.38% > > example4b > > > > 8600 > > > > 418 > > > > -95.14% > > example1 > > > > 6910 > > > > 360 > > > > -94.79% > > example7 > > > > 6025 > > > > 349 > > > > -94.21% > > example10b > > > > 919 > > > > 350 > > > > -61.92% > > example25 > > > > 932 > > > > 378 > > > > -59.44% > > example10a > > > > 933 > > > > 390 > > > > -58.20% > > example21 > > > > 6776 > > > > 7567 > > > > 11.67% > > example13 > > > > 1223 > > > > 1414 > > > > 15.62% > > example11 > > > > 7808 > > > > 10343 > > > > 32.47% > > example9 > > > > 7422 > > > > 10210 > > > > 37.56% > > example2b > > > > 6928 > > > > 9881 > > > > 42.62% > > example24 > > > > 797 > > > > 1441 > > > > 80.80% > > example14 > > > > 907 > > > > 1919 > > > > 111.58% > > example2a > > > > 785 > > > > 2053 > > > > 161.53% > > example5a > > > > 40 > > > > 214 > > > > 435.00% > > example23 > > > > 920 > > > > 6456 > > > > 601.74% > > example3 > > > > 938 > > > > 7164 > > > > 663.75% > > example4a > > > > 939 > > > > 7285 > > > > 675.83% > > example8 > > > > 123 > > > > 2518 > > > > 1947.15% > > ï¿½ > > On 01/24/2018 09:48 PM, Jin, Zheming wrote: > > The Microsoft Excelï¿½spread sheet lists the performance ofï¿½the > prototype compiler (anl) and the Intel CSA compiler (intel) > using the OpenMP mode and gcc-loops benchmark.ï¿½ï¿½ > > The performance metrics areï¿½cycles, static operation count and > static lic count.ï¿½ > > The test files are located > atï¿½/soft/restricted/intel_csa/apps/gcc-loops.ï¿½ > > ï¿½ > > ï¿½ï¿½imap://hfinkel%40anl%[email protected]:993/fetch%3EUID%3E/INBOX%3E1035759037?header=quotebody&part=1.2&filename=image001.png > > ï¿½ > > imap://hfinkel%40anl%[email protected]:993/fetch%3EUID%3E/INBOX%3E1035759037?header=quotebody&part=1.3&filename=image002.png > > ï¿½ > > imap://hfinkel%40anl%[email protected]:993/fetch%3EUID%3E/INBOX%3E1035759037?header=quotebody&part=1.4&filename=image003.png > > > > > > _______________________________________________ > > anl-intel-csa mailing list > > anl-intel-csa(a)lists.jlse.anl.gov > <mailto:[email protected]> > > https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa > > > > > -- > > Hal Finkel > > Lead, Compiler Technology and Programming Languages > > Leadership Computing Facility > > Argonne National Laboratory > > > > -- > Hal Finkel > Lead, Compiler Technology and Programming Languages > Leadership Computing Facility > Argonne National Laboratory -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark
by Sudarsanam, Arvind 25 Jan '18

25 Jan '18

Hi Hal, I tried blocked-distribution spmdization and the number of cycles is 512. No, the performance is not different from using cyclic-distribution. Thanks Arvind From: Hal Finkel [mailto:[email protected]] Sent: Thursday, January 25, 2018 12:46 PM To: Sudarsanam, Arvind <arvind.sudarsanam(a)intel.com>; Jin, Zheming <zjin(a)anl.gov>; anl-intel-csa(a)jlse.anl.gov Subject: Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark On 01/25/2018 11:38 AM, Sudarsanam, Arvind wrote: Hi, I looked at the very first example (example4c) and was able to reproduce the numbers presented here. I went ahead and annotated the loop inside example4c with the spmdization intrinsic and I was able to bring the intel compiler cycles to 504. Annotation: __builtin_csa_spmdization(8,"cyclic"); I can try other test cases as well. Thanks! Out of curiosity, because our prototype always uses block distribution (we haven't implemented cyclic yet), is the performance different with the Intel compiler with block-distribution spmdization? -Hal Thanks Arvind From: anl-intel-csa [mailto:[email protected]] On Behalf Of Hal Finkel Sent: Wednesday, January 24, 2018 11:15 PM To: Jin, Zheming <zjin(a)anl.gov><mailto:[email protected]>; anl-intel-csa(a)jlse.anl.gov<mailto:[email protected]> Subject: Re: [Anl-intel-csa] Evaluation of ANL Prototype Compiler using gcc-loops benchmark Zheming, thanks! It might be easier to look at it this way (negative means our prototype is better, positive means Intel's is better): cycles (intel) cycles (anl) intel speedup example4c 27089 440 -98.38% example4b 8600 418 -95.14% example1 6910 360 -94.79% example7 6025 349 -94.21% example10b 919 350 -61.92% example25 932 378 -59.44% example10a 933 390 -58.20% example21 6776 7567 11.67% example13 1223 1414 15.62% example11 7808 10343 32.47% example9 7422 10210 37.56% example2b 6928 9881 42.62% example24 797 1441 80.80% example14 907 1919 111.58% example2a 785 2053 161.53% example5a 40 214 435.00% example23 920 6456 601.74% example3 938 7164 663.75% example4a 939 7285 675.83% example8 123 2518 1947.15% On 01/24/2018 09:48 PM, Jin, Zheming wrote: The Microsoft Excel spread sheet lists the performance of the prototype compiler (anl) and the Intel CSA compiler (intel) using the OpenMP mode and gcc-loops benchmark. The performance metrics are cycles, static operation count and static lic count. The test files are located at /soft/restricted/intel_csa/apps/gcc-loops. [imap://hfinkel%40anl%[email protected]:993/fetch%3EUID%3E/INBOX%3E1035759037?header=quotebody&part=1.2&filename=image001.png] [imap://hfinkel%40anl%[email protected]:993/fetch%3EUID%3E/INBOX%3E1035759037?header=quotebody&part=1.3&filename=image002.png] [imap://hfinkel%40anl%[email protected]:993/fetch%3EUID%3E/INBOX%3E1035759037?header=quotebody&part=1.4&filename=image003.png] _______________________________________________ anl-intel-csa mailing list anl-intel-csa(a)lists.jlse.anl.gov<mailto:[email protected]> https://lists.jlse.anl.gov/mailman/listinfo/anl-intel-csa -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory -- Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Argonne National Laboratory

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