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[JLSE-Intel-NDA] Fwd: [lcf-staff] ALCF Seminar: Deep-Dive into the Intel Xeon Phi Processor
by Kumaran, Kalyan 20 Sep '16

20 Sep '16

If you are onsite at Argonne then this would be a very good seminar to attend especially if you are deep into code optimization for the KNL. -Kumar Begin forwarded message: From: "Doyle, Virginia M." <vdoyle(a)anl.gov<mailto:[email protected]>> Subject: [lcf-staff] ALCF Seminar: Deep-Dive into the Intel Xeon Phi Processor Date: September 20, 2016 at 8:12:55 AM CDT To: CPA Seminars <seminars(a)anl.gov<mailto:[email protected]>>, "seminars(a)mcs.anl.gov<mailto:[email protected]>" <seminars(a)mcs.anl.gov<mailto:[email protected]>>, "lcf-staff(a)alcf.anl.gov<mailto:[email protected]>" <lcf-staff(a)alcf.anl.gov<mailto:[email protected]>> Argonne Leadership Computing Facility Guest speaker: Alexander Heinecke, Intel Hosted by: Kalyan Kumaran, Deputy Director of Science - Advanced Technologies & Data Date: Monday, October 3, 2016 Time: 10:00 - 11:00 am Location: ANL, Building 240, TCS Conference Center 1404-05. Title: Deep-Dive into the Intel Xeon Phi Processor (formerly code-named Knights Landing) The purpose of this talk is to present architectural details of the Intel Xeon Phi Processor and to point out how to code for the Intel Xeon Phi processor. We will therefore discuss Xeon Phi's memory and cluster modes and their best usages as well as Xeon Phi's core design. This allows to point out differences and similarities compared to regular and well-known Intel Xeon processors. The talk will be closed by covering code motifs which yield high performance on the Xeon Phi Processor. _______________________________________________ lcf-staff mailing list lcf-staff(a)lists.alcf.anl.gov<mailto:[email protected]> https://lists.alcf.anl.gov/cgi-bin/mailman/listinfo/lcf-staff

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Re: [JLSE-Intel-NDA] MPI with GCC on KNL
by Childers, Taylor 20 Sep '16

20 Sep '16

Ah, I see. The Twiki only mentions the intel mpi compilers as coming from this source. Thanks. J. Taylor Childers, Assistant Physicist Argonne National Laboratory HEP Division Bldg. 360, Rm. C-217 Office: (630) 252-4212 Mobile: (331) 302-4647 jchilders(a)anl.gov<mailto:[email protected]> On Sep 20, 2016, at 8:44 AM, Tom LeCompte <lecompte(a)anl.gov<mailto:[email protected]>> wrote: source /soft/compilers/intel_beta/compilers_and_libraries/linux/bin/compilervars.sh intel64

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Re: [JLSE-Intel-NDA] MPI with GCC on KNL
by Tom LeCompte 20 Sep '16

20 Sep '16

Hi Taylor, source /soft/compilers/intel_beta/compilers_and_libraries/linux/bin/compilervars.sh intel64 mpicc gives you either GCC or something very very close. If the touchy code is Sherpa, this works, at least for a bare bones installation. Cheers, Tom On 9/20/2016 8:40 AM, Childers, Taylor wrote: > Hello, > > I have a particularly touchy code that I haven't been able to compile > yet with intel compilers and I'd like to use gcc for the KNL cluster. > > Is there a gcc/mpich installation somewhere I can use? > > Thanks, > Taylor > > > > > J. Taylor Childers, Assistant Physicist > Argonne National Laboratory > HEP Division Bldg. 360, Rm. C-217 > Office: (630) 252-4212 Mobile: (331) 302-4647 > jchilders(a)anl.gov <mailto:[email protected]> > > > > _______________________________________________ > Intel-nda mailing list > Intel-nda(a)lists.jlse.anl.gov > https://lists.jlse.anl.gov/mailman/listinfo/intel-nda

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[JLSE-Intel-NDA] MPI with GCC on KNL
by Childers, Taylor 20 Sep '16

20 Sep '16

Hello, I have a particularly touchy code that I haven't been able to compile yet with intel compilers and I'd like to use gcc for the KNL cluster. Is there a gcc/mpich installation somewhere I can use? Thanks, Taylor J. Taylor Childers, Assistant Physicist Argonne National Laboratory HEP Division Bldg. 360, Rm. C-217 Office: (630) 252-4212 Mobile: (331) 302-4647 jchilders(a)anl.gov<mailto:[email protected]>

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[JLSE-Intel-NDA] Reporting Intel compiler, tools bugs
by Kumaran, Kalyan 13 Sep '16

13 Sep '16

I have set up a generic account to report software bugs back to Intel. Login at premier.intel.com<http://premier.intel.com> Username: argonne-intel Password: ArgonneIntel16! Click on Intel Premier Support on the LHS panel. You should see the open Quad issues (basically a bug reported by Steve Pieper). Updates to the Quad issues are emailed to the mailing list argonne-intel(a)alcf.anl.gov<mailto:[email protected]> (yes, alcf domain). So you need to subscribe the list at: https://lists.alcf.anl.gov/mailman/listinfo/argonne-intel Be good about tracking your issue and providing feedback whenever Intel updates the quad. I will add this to our confluence site tomorrow. Thanks, Kumar P.S.: There might be an update to your Quad issue from Martyn.

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Re: [JLSE-Intel-NDA] No space left on garfunkel-b:/vol/ft_home
by Allen, Benjamin S. 12 Sep '16

12 Sep '16

We increased the capacity of ft_home a bit. We've had a project on the back burner to install a small dedicated NetApp filer for JLSE. We already have the hardware, but it needs to be moved physically and ft_home migrated to it. Depending on other project load I might get to this in the 3-4 week timeframe. It will give us quite a bit more room for ft_home and ft_soft. Ben > On Sep 12, 2016, at 3:31 PM, Delalondre Fabien Jonathan <fabien.delalondre(a)epfl.ch> wrote: > > Can some of us clean up some space ? :D > Thanks, > > Fabien > _______________________________________________ > Intel-nda mailing list > Intel-nda(a)lists.jlse.anl.gov > https://lists.jlse.anl.gov/mailman/listinfo/intel-nda

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[JLSE-Intel-NDA] No space left on garfunkel-b:/vol/ft_home
by Delalondre Fabien Jonathan 12 Sep '16

12 Sep '16

Can some of us clean up some space ? :D Thanks, Fabien

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Re: [JLSE-Intel-NDA] MKL KNL BLAS performance
by Hammond, Jeff R 11 Sep '16

11 Sep '16

Sent from my iPhone > On Sep 11, 2016, at 11:28 AM, Kenneth E Jansen <kenneth.jansen(a)colorado.edu> wrote: > > Does anyone know where I can find what the expected performance of level 1 and level 2 BLAS on KNL using MKL should be? BLAS1 is always BW-limited and you can compute performance as a function of bandwidth from the location in the memory hierarchy when it's called. BLAS2 also BW-limited in all cases I know about. > For now lets keep it simple > > DDOT n=O(10k) > DGEMV n=O(10k) and m O(100) called in “T” mode so that the fast/first index of the passed matrix is the one that is contracted with the vector x to create an m length y result. > > Benchmark or even personal experience would be useful. I know somewhere on one of the Wiki’s someone posted something like 1500GF/node for the 7210 for DGEMM so if anyone knows the comparable number for DDOT or DGEMV that would be great. If it is known how big n, and need to be to achieve the quoted number that would also be great. > DGEMM should hit at least 1.9 TF/s with the 7250s unless one sets KMP_AFFINITY wrong. > > In a related question, is there anything aside from adding -mkl to the compiler flags to get the code to use the AVX512 MKL code? This was enough to get correct results but is it enough to get best performance? > MKL will detect ISA at runtime. You can override to disable AVX-512 with env var but it's on by default on KNL. For BLAS1/BLAS2 code, I doubt AVX-512 helps that much except due to prefetch instructions. > Further followup, does Advisor or VTUNE have knowledge of what MKL is doing? I ask this because Advisor is telling me that dgemv and ddot are scalar and tells me I should use the vector form so I am kind of hoping that I am missing something but I recognize that Advisor may just not have the ability to gather that information and assumes external stuff is scalar? > That's just overzealous and incorrect advice. Please ignore. > I have asked this in the nda list. Is this sort of information still nda? > I will only share public info here unless it is clearly labeled otherwise. Jeff > Thanks for any help with even one of these questions. > > Best regards, > > Ken > > > ---------------------------------------------------------------- > Kenneth E. Jansen, Professor of Aerospace Engineering Sciences > ECAE 161 OFFICE (303) 492-4359 > 429 UCB FAX (303) 492-4990 > University of Colorado at Boulder jansenke(a)colorado.edu > Boulder, CO, 80309-0429 http://www.colorado.edu/aerospace > ---------------------------------------------------------------- > > > > _______________________________________________ > Intel-nda mailing list > Intel-nda(a)lists.jlse.anl.gov > https://lists.jlse.anl.gov/mailman/listinfo/intel-nda

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[JLSE-Intel-NDA] MKL KNL BLAS performance
by Kenneth E Jansen 11 Sep '16

11 Sep '16

Does anyone know where I can find what the expected performance of level 1 and level 2 BLAS on KNL using MKL should be? For now lets keep it simple DDOT n=O(10k) DGEMV n=O(10k) and m O(100) called in “T” mode so that the fast/first index of the passed matrix is the one that is contracted with the vector x to create an m length y result. Benchmark or even personal experience would be useful. I know somewhere on one of the Wiki’s someone posted something like 1500GF/node for the 7210 for DGEMM so if anyone knows the comparable number for DDOT or DGEMV that would be great. If it is known how big n, and need to be to achieve the quoted number that would also be great. In a related question, is there anything aside from adding -mkl to the compiler flags to get the code to use the AVX512 MKL code? This was enough to get correct results but is it enough to get best performance? Further followup, does Advisor or VTUNE have knowledge of what MKL is doing? I ask this because Advisor is telling me that dgemv and ddot are scalar and tells me I should use the vector form so I am kind of hoping that I am missing something but I recognize that Advisor may just not have the ability to gather that information and assumes external stuff is scalar? I have asked this in the nda list. Is this sort of information still nda? Thanks for any help with even one of these questions. Best regards, Ken ---------------------------------------------------------------- Kenneth E. Jansen, Professor of Aerospace Engineering Sciences ECAE 161 OFFICE (303) 492-4359 429 UCB FAX (303) 492-4990 University of Colorado at Boulder jansenke(a)colorado.edu Boulder, CO, 80309-0429 http://www.colorado.edu/aerospace ----------------------------------------------------------------

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Re: [JLSE-Intel-NDA] MCRAM/Memkind/Vtune questions
by Vitali Morozov 07 Sep '16

07 Sep '16

Hi Fabian, let us meet tomorrow at 10 am and try to understand the output. Vitali On 09/07/2016 05:22 PM, Delalondre Fabien Jonathan wrote: > > Hi All, > > > I am trying to benchmark and understand performance using Vtune memory > bandwidth analysis when allocating memory in DRAM and MCRAM explicitly > using both memkind and hbwmalloc interface (on a toy example). > > > The KNL config I used is FLAT/Quadrant. I am just using a single core > with 4 omp threads and I am not sure to understand the results I am > getting from vtune. > > > Who would feel kind enough and comfortable enough with Vtune to spend > 15-20min with me maybe tomorrow ? > > > Few questions: > > 1) Even though I allocate memory first in DRAM, then in MCDRAM (adding > a barrier between the two), Vtune seems to indicate DRAM/MCDRAM memory > bandwidth utilisation is overlapping as if it would read data from > both MCDRAM/DRAM at the same time. > > Note that I make sure to explicitly initialise memory to force the > allocation. > > 2) What's the difference between package and channel memory in this > context. I would expect the channel to be the memory channel > monitored. But then... if I am using a single core, why is the DRAM > package memory bandwidth different from the channel one... > > > Thanks for your help. > > > Fabien > > > > _______________________________________________ > Intel-nda mailing list > Intel-nda(a)lists.jlse.anl.gov > https://lists.jlse.anl.gov/mailman/listinfo/intel-nda

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