...

Ok, but, the kind of thing that delays that visibility (e.g. the uncertainty between when a posted write starts over PCIExpress and when it is known to be globally visible) is completely unaffected by a memory barrier. Memory barrier until your heart is content and that thing could still be getting retried across a PCIExpress link and the process (and the NIC and other side of the link and just about anything else) would have no way to know...

Hmm. Yes, you are right. That's even worse though :-(.

Not usually. If you start synchronizing outside the network you better know exactly what you are doing. Most networks have some ordering primitives to help here.